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16-Bit I/O Expander IC
PT8300
DESCRIPTION
PT8300 is an I/O expander utilizing CMOS technology providing 16 bits serial input-parallel output and 8 bits parallel input-serial output shift register function. 8 input pins or 16 output pins can be configured to a cascading or parallel structure. Reading of serial data during the parallel to serial data conversion is enabled by the built-in independent registers for serial input to parallel output and parallel input to serial output. Housed in 28 pins, SOP Package, PT8300 provides 8 input or 16 output pins which can be configured into a cascading structure. Pin assignments and application circuits are optimized for easy PCB layout and cost saving benefits.
FEATURES
* CMOS technology * Low power consumption: - Wide operating supply voltage range: VDD=3 to 5.5V - Wide operating temperature range: Ta=-20 to +75 * Reading of the serial data during parallel to serial data conversion * 8 output pins or 8 input/output pins provided * Schmitt triggered inputs (DI1,DI2,CLK,LATCH, /RESET,PULLUP) * Parallel data inputs provided (P8 to P15) * Open drain with selectable pull up resistance ports provided (P8 to P15) * Normal output ports provided (P0 to P7) * Port extension is supported
APPLICATIONS
* MCU peripheral device * Serial bus system data communication
PT8300 V1.8
-1-
February, 2006
PT8300 V1.8
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P4 P15
16-Bit I/O Expander IC
PULLUP
27
BLOCK DIAGRAM
VDD
28
VSS
1
-2LATCH RESET I0 Latch 16-Bit I7 O0 O7 O8 I8 CLK DI RESET Q0 CLK DI D0
LATCH
4
O15 I15
CLK
3
DI1
26 Shift Register 1: 16-Bit Shift Register Serial to Parallel Q15 DO
/RESET
2
14
CLKO DI2
16
Shift Register 2: 16-Bit Shift Register Parallel to Serial
D15 DO
LATCHO
13
DO2
25
DO1
15
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
February, 2006
PT8300
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
PIN CONFIGURATION
VSS /RESET CLK LATCH P15 P14 P13 P12 P11 P10 P9 P8 LATCHO CLKO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD PULLUP DI1 DO2 P0 P1 P2 P3 P4 P5 P6 P7 DI2 DO1
PT8300
PIN DESCRIPTION
Pin Name VSS /RESET CLK LATCH P15 ~ P8 LATCHO CLKO DO1, DO2 DI1, DI2 P7 ~ P0 PULLUP VDD I/O I I I I/O O O O I O I Description Ground Reset pin (Active: Low) Clock input pin Latch input pin Parallel data input/output pins Latch output pin Clock output pin Serial data output pins Serial data input pins Parallel data output pins P8 to P15 control pin for internal resistor When P8 to P15 are in the output state, the PULLUP pin must be connected to VDD. When P8 to P15 are in the input state, the PULLUP pin must be connected to VSS. Pin No. 1 2 3 4 5 ~ 12 13 14 15, 25 26, 16 17 ~ 24 27 28
PT8300 V1.8
-3-
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
FUNCTION DESCRIPTION
PT8300 is an I/O Expander IC which independently generates a 16-bit serial input-to-parallel output shift register and a parallel input-to-serial output shift register for the purpose of reading the serial input data that is generated during the parallel to serial data output conversion. When the /RESET Pin is connected to VSS, the outputs of pins -- P0 to P7 are 0. If the PULLUP pin is connected to VSS or open, the outputs of pins -- P8 to P15 are floating. If the PULLUP pin is connected to VDD, the P8 to P15 pins are 1.
NO USED PINS
If any of the Input, Output or I/O (P8 to P15) pins are not used, then the following conditions listed in the table must be carefully followed. When an output pin is not used, it must keep OPEN. The unused input pin must only be set to either HIGH or LOW. It should be noted that when an input pin is not used, it cannot be OPEN. When the I/O Pins -- P8 to P15 -- are not used, certain conditions must be followed. If any of these pins, P8 to P15 are connected to VSS, the PULLUP Pin must also be connected to VSS. If any of these pins -- P8 to P15 -- are connected to VDD, then the Internal Shift Register 1 (Q8 to Q15) must be set to 1. If these pins -- P8 to P15 -- are not connected to either VSS or VDD, then any one of the following conditions must be followed: 1) PULLUP pin must be connected to VDD and the Shift Register 1 (Q8 to Q15) must be set to 1, or 2) PULLUP pin must be connected to VSS and the Shift Register 1 (Q8 to Q15) must be set to 0. It must be noted that when P8 to P15 are not in used, they must be set to HIGH or LOW. Type of Pin Not Used Output pin Input pin Condition The unused output pin must be kept OPEN or not connected The unused input pin must either be set to HIGH or LOW. It cannot be kept OPEN. Connected to VSS PULLUP pin must be connected to VSS Connected to VDD Shift register 1 (Q1 to Q15) is set to 1 Any one of the conditions must be followed: 1. PULLUP pin is connected to VDD and shift register 1 (Q1 to Q15) is set to 1. No Connection 2. PULLUP pin is connected to VSS, and shift register 1 (Q8 to Q15) is set to 0. 3. When P8 to P15 are not in used, they must either be set to HIGH or LOW.
I/O pin (P8 to P15)
PT8300 V1.8
-4-
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
OPERATION
1. P0 to P15 are undefined when power is turned ON, but if /RESET is set to LOW, P0 to P7 are in LOW state. If PULLUP pin is connected to VSS, P8 to P15 are floating. If PULLUP pin is connected to VDD, P8 to P15 are in HIGH State. 2. The status of P0 to P15 is loaded to the Shift register 1 at the falling edge of LATCH/LATCHO. 3. At the falling edge of the CLK, the 16-bit serial output of the data loaded to the Shift register 1 (Shift register 2) is sequentially performed from DO1(DO2). 4. At the rising edge of CLK, 16-bit serial data is written into the Shift register 1 (Shift register 2) from DI1(DI2). 5. At the rising edge of the LATCH/LATCHO, the data written is outputted in a parallel manner to the P0 to P15. 6. Shift Register 1 loads the data that is to be applied externally and the data with the latched content. to the parallel output latch. 7. When the LATCH/LATCHO is activated after the arrival of CLK's 16th bit, the parallel output latch sends out P0 to P15 by storing the data that has been written into the Shift register 2. The Shift Registers 1 and 2 continue the shift operation until the CLK's 16th bit and the DO1 (DO2) output serial data arrive. 8. Serial data is used to control the switching mode operation (input output) of P8 to P15. When P8 to P15 operate as Output Pins, the PULLUP must be set to HIGH.
OPERATION TIMING DIAGRAM
/RESET LATCH/LATCHO CLK/CLKO DI1/DI2 DO1/DO2 P0 P1 P15
1 2 3 4 5 16
DI0
DI1
DI2
DI3
DI1 5
DO 0
DO 1
DO 2
DO 3
DO 1 5
DI0-1
DI0
DI1-1
DI1
DI15-1
DI1 5
PT8300 V1.8
-5-
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
TIMING REQUIRMENTS
(Unless otherwise stated, VCC=5V)
Parameter
CLK, LATCH, /RESET pulse width DI1/DI2 setup time for CLK Latch setup time for LK DI1/DI2 hold time for CLK LATCH hold time for CLK LATCH recovery time
Symbol
tw tSU tH tREC
Min. 100 50 50 50 50 50
Limits Ta=25, Ta=-40 ~ +85 Typ. Max. Min. Typ. 150 100 100 100 100 100 -
Unit Max. ns ns ns ns ns ns
TIMING DIRGRAM
CLK
tw 50 % tw 50 %
tw VCC 50 % tw VCC 50 % tw 50 % 50 % GND VCC 50 % 50 % tH 50 % 50 % tSU 50 % tH VCC 50 % GND VCC tREC GND VCC GND GND VCC GND VCC GND VCC GND 50 % GND
LATCH
50 %
/RESET DI1 to DI2
50 % 50 % tSU
CLK LATCH
CLK /RESET
50 %
LATCH
PT8300 V1.8
-6-
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
DATA TIMING DIAGRAM
READ
SINGLE MODE (P0-P7 = Output [Write], P8-P15 = Input [Read])
Latch
1 C LK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D I1
F F H (P 15 to P 8)
00H ~F F H (P7 to P 0)
D O2
P 15~P 8
IR RE LE VA N T
CASCADE MODE (P0-P7 [Master] = Output [Write], P8-P15 [Master] = Input [Read], P0-P7 [Slave] = Output [Write], P8-P15 [Slave] = Input [Read])
L a tc h
1
CLK
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DI1
F F H (Sl a ve P 1 5 to P 8 )
0 0 H ~ FF H ( Sl a ve P 7 t o P0 )
F F H (M a ste r P 1 5 to P 8 )
0 0 H ~ FF H ( Ma s te r P 7 to P0 )
DO2
P8 ~P1 5 (Ma s te r)
IR R EL E VA N T
P8 ~P1 5 (Sl a ve )
IR R EL E VA N T
PT8300 V1.8
-7-
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC WRITE
WRITE DATA
PT8300
LATC H
1 89 16
CLK DI1
P1 5 to P 8 P7 to P0
PT8300 V1.8
-8-
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
ABSOLUTE MAXIMUM RATING
(Unless otherwise specified, Topr=-40~+85) Parameter Symbol Supply voltage VDD Input voltage VI Output voltage VO Operation temperature Topr Storage temperature Tstg
Condition
-
Ratings -0.3 ~ 7.0 -0.3 ~ VCC+0.3 -0.3 ~ VCC+0.3 -40 ~ +85 -65 ~ +150
Unit V V V
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, VCC=2V to 6V) Parameter Symbol Condition Min. Supply voltage VCC 3.0 Stand-by current ISB VCC=3V, CLK=1MHz LATCH, /RESET connected to VDD. PULLUP, DI1, DI2 connected to GND Operating current IDD VCC=5V, CLK=1MHz LATCH, /RESET connected to VDD. PULLUP, DI1, DI2 connected to GND VCC=5V High level input voltage VIH (CLK, LATCH, DI1, 0.7VDD DI2, PULLUP) VCC=5V Low level input voltage VIL (CLK, LATCH, DI1, VSS DI2, PULLUP) VCC=5V (Output Pins other than P0 2.5 to P7, VOH=4.7V) High level output current IOH VCC=5V 0.5 (P8 to P15, VOH=4.7V) VCC=5V (Output Pins other than 3.5 P0 to P7, VOH=0.3V) Low level output current IOL VCC=5V 13 (P8 to P15, VOH=0.8V)
Typ. 50
Max. 5.5 1
-
Unit V A A
85
-
A
-
VDD 0.2VDD -
V V mA mA mA mA
PT8300 V1.8
-9-
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
SOP28 300 MIL THERMAL PERFORMANCE IN STILL AIR AT TJ=100OC
PT8300 V1.8
- 10 -
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
SSOP28 150 MIL THERMAL PERFORMANCE IN STILL AIR AT TJ=100OC
PT8300 V1.8
- 11 -
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
APPLICATION CIRCUIT 1
5V VDD VSS PULLUP /RESET CLK DI1 DO2 LATCH P15 P0 P1 P14 P13 P2 PT8300 P12 P3 P4 P11 P10 P9 P8 LATCHO CLKO P5 P6 P7 DI2 DO1
1 2 3 4 5 6 7
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P8 TO P15
8 9 10 11 12 13 14
P0 TO P7
MCU
PT8300 V1.8
- 12 -
February, 2006
PT8300 V1.8
5V VCC P0 P0 to OUTPUT P8 to P15 P7 P15 P7 LATCH CLK DI1 DO2 P15 LATCH CLK DI1 DO2 P0 to OUTPUT P8 to P15 P7 I/O PORT VCC I/O PORT P0 5V VCC P0 P7 5V VSS P8
16-Bit I/O Expander IC
I/O PORT
VSS P8
PT8300 PT8300
VSS P8
P8 to P15
NEXT PT8300
APPLICATION CIRCUIT 2
P0 to OUTPUT P7
P15
- 13 PULLUP LATCHO CLKO DO1 DI2 /RESET PULLUP
LATCH CLK DI1 DO2
M A P7 S LATCHO T CLKO DO1 E DI2 R /RESET
S L A V E
LATCHO CLKO DO1 DI2 /RESET PULLUP
MCU
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
February, 2006
PT8300
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
ORDER INFORMATION
Valid Part Number PT8300 PT8300-R Package Type 28 Pins, SOP, 300mil 28 Pins, SSOP, 150mil Top Code PT8300 PT8300-R
PT8300 V1.8
- 14 -
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
PACKAGE INFORMATION
28 PINS, SOP, 300MIL
Symbol A A1 B C D E e H h L
Min. Max 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 7.40 7.60 1.27 bsc 10.00 10.65 0.25 0.75 0.40 1.27 o 0 8o
PT8300 V1.8
- 15 -
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
Notes: 1. Dimensioning and tolerancing per ANSI Y14.5-1982. 2. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006 in) per side. 3. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusion shall not exceed 0.15mm (0.016in) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. L is the length of terminal for soldering to a substrate. 6. N is the number of terminal positions (N=28). 7. The lead width B as measured 0.36mm (0.014in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024 in). 8. Controlling dimension: MILLIMETER 9. Refer to JEDEC MS-013 Variation AE. JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
PT8300 V1.8
- 16 -
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
28 PINS, SSOP, 150MIL
PT8300 V1.8
- 17 -
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
PT8300 V1.8
- 18 -
February, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
Symbol
A A1 A2 b c D E E1 e L L1 R R1 1 2
PT8300
Dimension in Inches Typ. 0.390 BSC. 0.236 BSC. 0.154 BSC. 0.025 BSC. 0.041 REF. -
Min. 0.053 0.004 0.049 0.008 0.006
Max. 0.069 0.010 0.065 0.012 0.010
0.016 0.003 0.003 0 5 0
0.050 8 15 -
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions in Inches (Angles in Degrees) 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches per end. Dimension E1 does not include interlead flashor protrusion. Interlead flash or protrusion shall not exceed 0.006 inches per side. D and E1 dimensions are determined at datum H. 4. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 5. Datums A & B to be determined at datum H. 6. The dimensions apply to the flat section of the lead between 0.004 to 0.010 inches from the lead tip. 7. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.004 inches total in excess of the b dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. 8. Refer to JEDEC MO-137 Variation AF JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT8300 V1.8
- 19 -
February, 2006

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